1. Field of the Invention
Embodiments of the present invention relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to a process for depositing dielectric layers on a substrate.
2. Description of the Related Art
Integrated circuit geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication facilities are routinely producing devices having 0.13 μm and even 0.1 μm feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes.
The continued reduction in device geometries has generated a demand for films having lower k values because the capacitive coupling between adjacent metal lines must be reduced to further reduce the size of devices on integrated circuits. In particular, insulators having low dielectric constants (k), less than about 4.0, are desirable. Examples of insulators having low dielectric constants include spin-on glass, such as un-doped silicon glass (USG) or fluorine-doped silicon glass (FSG), silicon dioxide, and polytetrafluoroethylene (PTFE), which are all commercially available.
While dielectric materials having dielectric constants of less than 4 have been developed, dielectric materials having lower dielectric constants, such as less than about 2.5 are desired. There is a need, therefore, for a controllable process for making lower dielectric constant materials to improve the speed and efficiency of devices on integrated circuits.